Download PDF:
ITEC220_221.pdf
Credit Hours: 2
Instructors:
Location:
Semester: Spring 2003
Course Description:
ITEC 220 Introduction to Digital Systems/VHD
Students are introduced to Boolean algebra and logic circuits. Combinational circuits and synchronous sequential circuits are studied with an emphasis on the electronic aspects of digital circuits design.
ITEC 221 Design of COMB/SEQ Circuits
Advanced techniques for designing combinatorial circuits and asynchronous sequential circuits are introduced with a discussion of a number of practical issues that arise in the design and test of real systems.
Course Objectives:
ITEC 220
- Explain fundamentals of Boolean Algebra.
- Describe VLSI design methodology & associated tools.
- Analyze and minimize combinatorial circuits.
- Describe the logical structure and operation of sequential circuits.
- Analyze and design simple Finite State machines.
ITEC 221
- Explain the logic and structure of Arithmetic Circuits.
- Analyze and design Code Conversion Circuits.
- Explain Synchronous Logic design characteristics and methodology.
- Understand and make good use of VHDL functions.
- Work out typical design problems and issues.
Delivery Method:
Presentational Cooperative (PC)
In this course delivery model students meet once per week to participate in cooperative learning activities facilitated by an instructor. Learning that would traditionally occur in a lecture is instead supported in a Web presentation that includes multimedia and interactive elements. The Presentational Cooperative Model reproduces most of the cost advantages of traditional lecture course while offering students more convenient access and more effective conditions for learning. Courses using this model will build the collaborative work skills that are a primary learning goal for SFU Students. Some courses, using this model, offer an optional Open Lab where students can receive additional learning support. Assessment may be based on individual and group assignments, quizzes, projects, and examinations.
Learning Activities + Evaluation:
*Please note these are the minimum expectations for each course on a weekly basis.
ALL:
Online/Text Reading: 2 hrs
Assignments: 2 hrs
Experiments: 2 hrs
Lab Projects: 2 hrs
Methods of Evaluation
ALL:
Exam: 40%
Assignments: 40%
Participation: 20%
Texts, Resources + Materials:
Text: Fundamentals of Digital Logic with VHDL Design,
Stephen Brown and Zvonko Vranesic, McGraw-Hill
Software: MAX+plus II from Altera (comes with the text)
Platform Requirements: PC
Prerequisites:
ALL: TECH 147 recommended, but not required for 2002/2003 Academic Year
ITEC 221: ITEC 220
Last Updated: May 13, 2008
These course outlines are drafts and are subject to change.
